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This circuit conditions different signals of frequency below 1 kHz and displays their waveforms on the PC’s screen. The hardware is used to condition the input waveform and convert it to the digital format for interfacing to the PC. The software for acquiring the data into the PC and displaying the same on its screen is written in Turbo C. The input waveform (limited to 5V peak-to-peak) is first applied to a full-wave rectifier comprising op-amps A1 and A2 of quad op-amp LM324 (IC4) and a zerocrossing detector built around LM3914 dot/ bar display driver (IC8) simultaneously. The full-wave rectifier rectifies the in- SANI THEO put signal such that the negative half cycle of the input signal is available in the positive side itself, so both the half cycles are read as positive when it is given as input to the ADC. During positive half cycle, diode D3 is on and diode D4 is off, and op-amps A1 and A2 act as inverters. Thus the output is a replica of the input. During the negative half cycle, diode D3 is off and diode D4 is on. With R2=R3=R4=R5=R6=R=330 ohms, the voltage (V) at inverting pin 2 of op-amp A1 is related to the input voltage (Vi) as follows: Vi/R +V/(2R)+V/R=0 V= -(2/3) The final output voltage (Vo) at pin 7 of op-amp A2 is given by the following relationship: Vo=(1+R/2R)(-2Vi/3)= -Vi As Vi is negative, the output voltage is positive. The zero-crossing detector detects whether the cycle is positive or negative. It is the most critical part of the circuit and if it operates improperly, the symmetry of the analogue signal displayed in the PC monitor gets affected. At the zero-crossing instant when the input signal transits to negative side, the zero-crossing detector informs the PC by taking pin 15 of 25- pin ‘D’ connector of the parallel port high. The input at pin 15 of ‘D’ connector goes low when the input signal transits to positive side. The zero-crossing detector communicates with the PC through bit D3 of the status port 379Hex. The zero-crossing detector has been realised using LM3914 IC. You may adjust VR1 such that the last LED (LED10) goes off when the input signal transits negative side of the input waveform. The LM3914 itself rectifies the input signal and allows only positive half of the cycle. The output from the full-wave rectifier is applied to the input of a sample-and-hold circuit comprising op-amps A3 and A4 of the LM324 (IC5), capacitor C3, transistor T1 (SL100), and analogue switch IC6 (CD4016). This circuit samples the input signal, i.e. it divides the waveform into a number of voltages or points and inputs each voltage level (with a delay) to the ADC for conversion into the digital format. Op-amps A3 and A4, along with a switch from IC CD4016 and a 1500pF capacitor with sampling time of 20 µs, are used as voltage followers/buffers. When the base of transistor T1 is made low via strobe pin 1 (bit Do of I/O port 37A) of 25-pin D connector of the parallel port, the transistor stops conducting and the voltage at its collector goes high. The high voltage at the collector of transistor T1 closes the switch inside CD4016. As a consequence, the analogue input signal is applied to the capacitor, which charges towards the signal voltage. When the switch is subsequently opened by applying a logic-high voltage from pin 1 of ‘D’ connector to the base of transistor T1, the capacitor retains the voltage with a loss of about 20 mV/sec and this voltage is given to input pin 6 of the ADC0804 (IC3) via buffer A4 for conversion to the digital format. When the number of sampling points in the input signal waveform is increased, the reconstructed waveform becomes more accurate. The ADC0804 is compatible with microprocessors. It is a 20-pin IC that works with 5V supply. It converts the analogue input voltage to 8-bit digital output. The data bus is tristate buffered. With eight bits, the resolution is 5V/255 = 19.6 mV. The inbuilt clock generator circuit produces a frequency of about 640 kHz with R1=10 kilo-ohms and C4=150 pF, which are the externally connected timing components. The conversion time obtained is approximately 100 µs. The functions of other pins are given below: Pin 1 (CS): This is activelow chip-select pin. Pin 2 (RD): This active-low pin enables the digital output buffers. When high, the 8-bit bus will be in Hi-Z state. Pin 3 (WR): This active-low pin is used to start the conversion. Pin 9 (Vref/2): This is optional input pin. It is used only when the input signal range is small. When pin 9 is at 2V, the range is 0-4V, i.e. twice the voltage at pin 9. Pin 6 (V+), Pin 7(V-): The actual input is the difference in voltages applied to these pins. The analogue input can range from 0 to 5V. In this circuit, pins 1 and 2 are always made low, so the IC and the buses are always enabled. Pin 9 is made open, as we use analogue input with 0-5V range. Pin 7 is grounded. Pin 5 (INTR): This active-low pin indicates the end of conversion. It is connected to pin 17 (bit D3 of I/O port 37A) of ‘D’ connector. (Note that this bit is inverted.) The start-of-conversion command via pin 16 of ‘D’ connector is applied to pin 3 of the ADC0804. Since we cannot read 8- bit digital data output from ADC through the 4-bit status port at a time, we divide it in two 4-bit parts and read. Hence the ADC data output is multiplexed through two 4-bit sections of octal buffers of IC1 (74244) with the help of output-enable signals from pins 2 and 9 of ‘D’ connector to pins 1 and 19 (OE1 and OE2, respectively) of IC1. The digital data output from IC1 is interfaced to the PC via pins 13 (D4), 12 (D5), 10 (D6), and 11 (D7) of status input port 379H of ‘D’ connector. The circuit uses 9V and 5V regulated DC supply voltages as shown in the circuit diagram. A PC printer port is an inexpensive platform for implementing low-frequency data acquisition projects. Each printer port consists of data, status, and control port addresses. These addresses are in sequential order; for example, if the data port address is 0x0378, the corresponding status port address is 0x0379 and the control port address is 0x037a. The port addresses for parallel ports are summarised below: (EFY Lab note. For details of the parallel port pins, refer ‘PC-based Dial Clock with Timer’ project published in June 2002 issue of EFY.) The software, written in C programming language, is user-friendly and easyto- understand. It gets data from the developed hardware circuit and displays it in the graphical screen with some changes. The C program includes two user-defined functions with the main function: graphics( ) and settings( ). The settings( ) function is used to adjust the voltage and time scale. The graphics( ) function is used to display the waveform on the screen. The sample control signal is used to close the switch in the sample-and-hold circuit, so the capacitor charges towards the analogue input voltage. After the sampling is over, the switch is opened using the same signal. Then the start-of-conversion control signal is given to start the conversion. The sampling time is approximately 20 µs and the conversion time is approximately 100 µs. After the conversion is over, the 8-bit binary data for the specific voltage sample is available in the data bus of the ADC. Since the PC accepts only 4-bit data through the status port (379H), the 8-bit data must be split into two 4-bit data, which are accepted one after another. This is done by IC 74244, which is controlled by D0 and D7 bits of the data port. Then the two 4-bit data are packed to get the final 8-bit data. The default BGI directory path is set as ‘c:\tc\bgi’. The sampling time is decided by the ‘for’ loop that uses the samp value. The maximum delay produced should be greater than 20 µs, which is the maximum acquisition time of the capacitor. When the sample value is increased, the number of points on the input signal decreases and therefore the accuracy decreases. The time scale may be calibrated with 50Hz sine wave as reference. This circuit costs around Rs 400.